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843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 1 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary g eneral d escription the ICS843101I-100 is a low phase-noise frequency margining synthesizer with fre- quency margining capability and is a member of the hiperclocks? family of high performance clock solutions from ics. in the default mode, the device nominally generates a 100mhz lvpecl output clock signal from a 24mhz crystal input. there is also a frequency margining mode available where the device can be programmed, using the serial interface, to vary the output frequency up or down from nominal in 2% steps. the ICS843101I-100 is provided in a 16-pin tssop. f eatures ? 100mhz nominal lvpecl output ? selectable crystal oscillator interface designed for 24mhz, 18pf parallel resonant crystal or lvcmos/lvttl single-ended input ? output frequency can be varied in 2% steps from nominal ? vco range: 540mhz - 680mhz ? rms phase jitter @ 100mhz, using a 24mhz crystal (1.875mhz - 20mhz): 0.55ps (typical) ? output supply modes core/output 3.3v/3.3v 3.3v/2.5v 2.5v/2.5v ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs-complaint packages hiperclocks? ic s p in a ssignment v ee s_load s_data s_clock sel oe v cca v cc 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 mode v cco q nq v ee clk xtal_out xtal_in ICS843101I-100 16-lead tssop 4.4mm x 5.0mm x 0.92mm package body g package top view b lock d iagram 11 0 phase detector vco 540 - 680mhz m osc n p serial control q nq pullup pulldown pulldown pulldown pulldown pulldown oe clk sel s_clock s_data s_load mode xtal_in xtal_out pulldown 24mhz the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specifications without notice.
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 2 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary f unctional d escription the ICS843101I-100 features a fully integrated pll and therefore requires no external components for setting the loop bandwidth. a 24mhz fundamental crystal is used as the input to the on chip oscillator. the output of the oscilla- tor is fed into the pre-divider. in frequency margining mode, the 24mhz crystal frequency is divided by 2 and a 12mhz reference frequency is applied to the phase detector. the vco of the pll operates over a range of 540mhz to 680mhz. the output of the m divider is also applied to the phase detector. the default mode for the ICS843101I-100 is 100mhz output frequency using a 24mhz crystal. the output frequency can be changed by placing the device into the margining mode using the mode pin and using the serial interface to program the m feedback divider. frequency margining mode operation occurs when the mode input is high. the phase detector and the m divider force the vco output fre- quency to be m times the reference frequency by adjusting the vco control voltage. note that for some values of m (either too high or too low), the pll will not achieve lock. the output of the vco is scaled by an output divider prior to being sent to the lvpecl output buffer. the divider provides a 50% output duty cycle. the relationship between the crys- tal input frequency, the m divider, the vco frequency and the output frequency is provided in table 1. when changing back from frequency margining mode to nominal mode, the device will return to the default nominal configuration that will provide 100mhz output frequency. serial operation occurs when s_load is high. serial data can be loaded in either the default mode or the frequency margining mode. the 6-bit shift register is loaded by samp- ling the s_data bits with the rising edge of s_clock. after shifting in the 6-bit m divider value, s_load is transitioned from high to low which latches the contents of the shift-register into the m divider control register. when s_load is low, any transitions of s_clock or s_data are ignored. t able 1. f requency m argin f unction t able f igure 1. s erial l oad o perations time s erial l oading t s t h m5 m4 m3 m2 m1 m0 t s s_clock s_data s_load l a t x ) z h m ( r e d i v i d - e r p ) p ( e c n e r e f e r ) z h m ( y c n e u q e r f k c a b d e e f ) m ( r e d i v i d a t a d - m ) y r a n i b ( o c v ) z h m ( t u p t u o ) n ( r e d i v i d t u p t u o y c n e u q e r f ) z h m ( e g n a h c % 4 22 2 15 41 0 1 1 0 10 4 56 0 90 . 0 1 - 4 22 2 16 40 1 1 1 0 12 5 56 2 90 . 8 - 4 22 2 17 41 1 1 1 0 14 6 56 4 90 . 6 - 4 22 2 18 40 0 0 0 1 16 7 56 6 90 . 4 - 4 22 2 19 41 0 0 0 1 18 8 56 8 90 . 2 - 4 22 2 10 50 1 0 0 1 10 0 66 0 0 1e d o m l a n i m o n 4 22 2 11 51 1 0 0 1 12 1 66 2 0 10 . 2 4 22 2 12 50 0 1 0 1 14 2 66 4 0 10 . 4 4 22 2 13 51 0 1 0 1 16 3 66 6 0 10 . 6 4 22 2 14 50 1 1 0 1 18 4 66 8 0 10 . 8 4 22 2 15 51 1 1 0 1 10 6 66 0 1 10 . 0 1
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 3 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary t able 2. p in d escriptions t able 3. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r p u l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ? ? ? 2 1 , 1v e e r e w o p. s n i p y l p p u s e v i t a g e n 2d a o l _ st u p n in w o d l l u p . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i l a i r e s e h t f o n o i t a r e p o e h t s l o r t n o c 3a t a d _ st u p n in w o d l l u p . k c o l c _ s f o e g d e g n i s i r e h t n o d e l p m a s a t a d . t u p n i l a i r e s r e t s i g e r t f i h s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 4k c o l c _ st u p n in w o d l l u p e h t n o r e t s i g e r t f i h s e h t o t n i t u p n i a t a d _ s t a t n e s e r p a t a d l a i r e s n i k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s f o e g d e g n i s i r 5l e st u p n in w o d l l u p . t u p n i k l c s t c e l e s , h g i h n e h w . n i p t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p n i l a t x s t c e l e s , w o l n e h w 6e ot u p n ip u l l u p . s t u p t u o q n / q f o g n i l b a s i d d n a g n i l b a n e s l o r t n o c . n i p e l b a n e t u p t u o s l e v e l e c a f r e t n i l t t v l / s o m c v l 7v a c c r e w o p. n i p y l p p u s g o l a n a 8v c c r e w o p. n i p y l p p u s e r o c 0 1 , 9 , n i _ l a t x t u o _ l a t x t u p n i e h t s i n i _ l a t x , t u p t u o e h t s i t u o _ l a t x . e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a p . t u p n i 1 1k l ct u p n in w o d l l u p. t u p n i k c o l c l t t v l / s o m c v l 4 1 , 3 1q , q nt u p u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 1v o c c r e w o p. n i p y l p p u s t u p t u o 6 1e d o mt u p n in w o d l l u p . e d o m g n i n i g r a m y c n e u q e r f = h g i h . e d o m t l u a f e d = w o l . n i p e d o m . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 4 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary t able 4d. s erial m ode f unction t able t able 4a. oe c ontrol i nput f unction t able t able 4b. sel c ontrol i nput f unction t able t able 4c. m ode c ontrol i nput f unction t able t u p n i l e se c r u o s d e t c e l e s 0t u o _ l a t x , n i _ l a t x 1k l c t u p n is t u p t u o e oq n , q 0z i h 1d e l b a n e t u p n in o i t i d n o c e d o mq n , q 0e d o m t l u a f e d 1e d o m g n i n i g r a m y c n e u q e r f s t u p n i s n o i t i d n o c d a o l _ sk c o l c _ sa t a d _ s lx x . d e r o n g i e r a s t u p n i l a i r e s h a t a d . e d o m t u p n i l a i r e s . k c o l c _ s f o e g d e g n i s i r h c a e n o a t a d _ s n o a t a d h t i w d e d a o l s i r e t s i g e r t f i h s lx . d e h c t a l e r a r e t s i g e r t f i h s e h t f o s t n e t n o c w o l = l : e t o n h g i h = h e r a c t ' n o d = x n o i t i s n a r t e g d e g n i s i r = n o i t i s n a r t e g d e g n i l l a f =
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 5 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary t able 5a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 89c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 2 9a m i c c t n e r r u c y l p p u s e r o c 8 7a m i a c c t n e r r u c y l p p u s g o l a n a 7a m i o c c t n e r r u c y l p p u s t u p t u o 4a m t able 5b. p ower s upply dc c haracteristics , v cc = v cca = 3.3v5%,v cco = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i e e t n e r r u c y l p p u s r e w o p 0 9a m i c c t n e r r u c y l p p u s e r o c 8 7a m i a c c t n e r r u c y l p p u s g o l a n a 7a m i o c c t n e r r u c y l p p u s t u p t u o 4a m t able 5c. p ower s upply dc c haracteristics , v cc = v cca = v cco = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 7 3 . 25 . 25 2 6 . 2v v a c c e g a t l o v y l p p u s g o l a n a 5 7 3 . 25 . 25 2 6 . 2v v o c c e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i e e t n e r r u c y l p p u s r e w o p 4 8a m i c c t n e r r u c y l p p u s e r o c 4 7a m i a c c t n e r r u c y l p p u s g o l a n a 7a m i o c c t n e r r u c y l p p u s t u p t u o 3a m
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 6 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary t able 6. c rystal c haracteristics t able 5d. lvcmos / lvttl dc c haracteristics , t a = -40c to 85c t able 5e. lvpecl dc c haracteristics , t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 - r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 4 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 0 0 1w . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n t able 7. i nput f requency c haracteristics , t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i t u p n i y c n e u q e r f k l c 4 2z h m t u o _ l a t x / n i _ l a t x 4 2z h m k c o l c _ s 0 5z h m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i v c c v 3 . 3 =2v c c 3 . 0 +v v c c v 5 . 2 =7 . 1v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i v c c v 3 . 3 =3 . 0 -8 . 0v v c c v 5 . 2 =3 . 0 -7 . 0v i h i t u p n i t n e r r u c h g i h , l e s , k l c , k c o l c _ s , d a o l _ s e d o m , a t a d _ s v c c v = n i 5 6 4 . 3 = v 5 2 6 . 2 r o 0 5 1a e o v c c v = n i 5 6 4 . 3 = v 5 2 6 . 2 r o 5a i l i t u p n i t n e r r u c w o l , l e s , k l c , k c o l c _ s , d a o l _ s e d o m , a t a d _ s v c c , v 5 2 6 . 2 r o v 5 6 4 . 3 = v n i v 0 = 5 -a e o v c c , v 5 2 6 . 2 r o v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a / t v n o i t s i s n a r t t u p n i e t a r l l a f / e s i r , l e s , e o , a t a d _ s , k c o l c _ s e d o m , d a o l _ s 0 2v / s n
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 7 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary t able 8a. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -40c to 85c t able 8b. ac c haracteristics , v cc = v cca = 3.3v5%,v cco = 2.5v5%, t a = -40c to 85c t able 8c. ac c haracteristics , v cc = v cca = v cco = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 0 1z h m t ) ? ( t i j1 e t o n ; r e t t i j e s a h p s m r w o l = e d o m ) z h m 0 2 - z h m 5 7 8 . 1 ( , z h m 0 0 1 5 5 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 25 7 4s p c d oe l c y c y t u d t u p t u o 0 5% t s e m i t p u t e s o t a t a d _ s k c o l c _ s 0 1s n k c o l c _ s d a o l _ s o t 0 1s n t h e m i t d l o h o t a t a d _ s k c o l c _ s 0 1s n . l a t s y r c z h m 5 2 a g n i s u d e z i r e t c a r a h c : 1 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 0 1z h m t ) ? ( t i j1 e t o n ; r e t t i j e s a h p s m r w o l = e d o m ) z h m 0 2 - z h m 5 7 8 . 1 ( , z h m 0 0 1 5 5 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 22 4 4s p c d oe l c y c y t u d t u p t u o 0 5% t s e m i t p u t e s o t a t a d _ s k c o l c _ s 0 1s n k c o l c _ s d a o l _ s o t 0 1s n t h e m i t d l o h o t a t a d _ s k c o l c _ s 0 1s n . l a t s y r c z h m 5 2 a g n i s u d e z i r e t c a r a h c : 1 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 0 1z h m t ) ? ( t i j1 e t o n ; r e t t i j e s a h p s m r w o l = e d o m ) z h m 0 2 - z h m 5 7 8 . 1 ( , z h m 0 0 1 5 5 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 25 0 4s p c d oe l c y c y t u d t u p t u o 0 5% t s e m i t p u t e s o t a t a d _ s k c o l c _ s 0 1s n k c o l c _ s d a o l _ s o t 0 1s n t h e m i t d l o h o t a t a d _ s k c o l c _ s 0 1s n . l a t s y r c z h m 5 2 a g n i s u d e z i r e t c a r a h c : 1 e t o n
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 8 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary o ffset f requency (h z ) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m t ypical p hase n oise at 100mh z (3.3v) 100mhz rms phase noise jitter 1.875mhz to 20mhz = 0.55ps (typical) ? ? ? 10 gigabit ethernet filter raw phase noise data phase noise result by adding 10 gigabit ethernet filter to raw data dbc hz n oise p ower
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 9 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary p arameter m easurement i nformation t pw t period t pw t period odc = x 100% q 2.5v c ore /2.5v o utput l oad ac t est c ircuit 3.3v c ore /2.5v o utput l oad ac t est c ircuit 3.3v c ore /3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.3v 0.165v rms p hase j itter clock outputs 20% 80% 80% 20% t r t f v sw i n g v cc , v cca , v cco v ee nq o utput d uty c ycle /p ulse w idth /p eriod phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power o utput r ise /f all t ime scope qx nqx lvpecl 2.8v0.04v -0.5v 0.125v v cc , v cca v ee v cco 2v scope qx nqx lvpecl 2v -0.5v 0.125v v cc , v cca , v cco v ee
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 10 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ICS843101I-100 pro- vides separate power supplies to isolate any high switch- ing noise from the outputs to the internal pll. v cc , v cca , and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 2 illustrates how a 10 resistor along with a 10f and a .01 f bypass capacitor should be connected to each v cca . the 10 resis- tor can also be replaced by a ferrite bead. p ower s upply f iltering t echniques f igure 2. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v or 2.5v .01 f v cc c rystal i nput i nterface the ICS843101I-100 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 3 below were determined using a 24mhz, 18pf par- figure 3. c rystal i npu t i nterface allel resonant crystal and were chosen to minimize the ppm error. c1 27p x1 18pf parallel crystal c2 27p xtal_out xtal_in
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 11 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary t ermination for 3.3v lvpecl o utput v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical ter- mination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. there- fore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination outputs are designed to drive 50 transmission lines. matched impedance techniques should be used to maxi- mize operating frequency and minimize signal distor- tion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compat- ibility across all printed circuit and clock component pro- cess variations. i nputs : c rystal i nput : for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. clk i nput : for applications not requiring the use of the test clock, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the clk input to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 12 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary t ermination for 2.5v lvpecl o utput figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 4b can be eliminated and the termination is shown in figure 4c. f igure 5c. 2.5v lvpecl t ermination e xample f igure 5b. 2.5v lvpecl d river t ermination e xample f igure 5a. 2.5v lvpecl d river t ermination e xample r2 62.5 zo = 50 ohm r1 250 + - 2.5v 2,5v lvpecl driv er r4 62.5 r3 250 zo = 50 ohm 2.5v vcc=2.5v r1 50 r3 18 zo = 50 ohm zo = 50 ohm + - 2,5v lvpecl driver vcc=2.5v 2.5v r2 50 2,5v lvpecl driv er vcc=2.5v r1 50 r2 50 2.5v zo = 50 ohm zo = 50 ohm + -
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 13 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS843101I-100. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS843101I-100 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 92ma = 318.78mw ? power (outputs) max = 30mw/loaded output pair total power _max (3.63v, with all outputs switching) = 318.78mw + 30mw = 348.78mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.349w *81.8c/w = 113.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 137.1c/w 118.2c/w 106.8c/w multi-layer pcb, jedec standard test boards 89.0c/w 81.8c/w 78.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 7. t hermal r esistance ja for 16- pin tssop, f orced c onvection
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 14 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 5. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 5. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 15 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary r eliability i nformation t ransistor c ount the transistor count for ICS843101I-100 is: 4093 t able 9. ja vs . a ir f low t able for 16 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard t est boards 137.1c/w 118.2c/w 106.8c/w multi-layer pcb, jedec standard test boards 89.0c/w 81.8c/w 78.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 16 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary p ackage o utline - g s uffix for 20 l ead tssop t able 10. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n6 1 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 40 1 . 5 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
843101agi-100 www.icst.com/products/hiperclocks.html rev. a october 20, 2005 17 integrated circuit systems, inc. ICS843101I-100 f emto c locks ? c rystal - to -lvpecl 100mh z f requency m argining s ynthesizer preliminary t able 11. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extr aordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademarks, hiperclocks and femtoclocks are trademarks of integrated circuit systems, inc. or its subsidiari es in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 0 0 1 - g a i 1 0 1 3 4 8 s c id b tp o s s t d a e l 6 1e b u tc 5 8 o t c 0 4 - t 0 0 1 - g a i 1 0 1 3 4 8 s c id b tp o s s t d a e l 6 1l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l 0 0 1 - g a i 1 0 1 3 4 8 s c id b tp o s s t " e e r f - d a e l " d a e l 6 1e b u tc 5 8 o t c 0 4 - t f l 0 0 1 - g a i 1 0 1 3 4 8 s c id b tp o s s t " e e r f - d a e l " d a e l 6 1l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n i a l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n

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